As semiconductor devices become more highly integrated, the size of the active region of the device on which circuits are formed becomes smaller. As a result, the channel length of a MOS transistor that is formed on the active region is reduced. It will be understood by those having skill in the art that as used herein, the term “MOS” refers to any insulated gate field effect transistor, the gate of which comprises metal and/or nonmetal (such as polysilicon) and the insulator of which comprises oxide and/or other insulators (such as high dielectric constant insulators).
As the channel length of the MOS transistor is reduced, the source and drain may have an increased effect on the electric field/electric potential in the channel region. This phenomenon is referred to as the short channel effect. Additionally, when the width of the channel is narrowed as the size of the active region is reduced, the threshold voltage of the MOS transistor may be lowered. This phenomenon is referred to as a reverse narrow width effect.
Methods for reducing the size of semiconductor devices and for improving the performance of such devices have been developed. For example, U.S. Pat. No. 6,413,802 discloses methods for providing a vertical MOS transistor having a fin structure that comprises a plurality of thin channel fins between a pair of source/drain regions and a gate electrode that is formed on both sides of the channel fins. U.S. Pat. No. 4,996,574 discloses a MOS transistor having a DELTA structure that has a channel layer that includes a vertically protruded portion which is surrounded by a gate electrode. MOS transistor having a gate all around (GAA) structure have also been proposed. In these transistors, an active pattern as an SOI layer may be formed on a substrate. A gate electrode surrounds the channel region of the active pattern, on which an insulation layer is formed.